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october 1993 order number: 271089-006 M80C196KB 16-bit high performance chmos microcontroller military y 232 byte register file y register-to-register architecture y 28 interrupt sources/16 vectors y 2.3 m s 16 x 16 multiply (12 mhz) y 4.0 m s 32/16 divide (12 mhz) y powerdown and idle modes y five 8-bit i/o ports y 16-bit watchdog timer y dynamically configurable 8-bit or 16-bit buswidth y available in 68-lead pga and 68-lead ceramic quad flat pack y full duplex serial port y high speed i/o subsystem y 16-bit timer y 16-bit up/down counter with capture y pulse-width-modulated output y four 16-bit software timers y 10-bit a/d converter with s/h y 12 mhz version e M80C196KB y available in two product grades: e mil-std-883, b 55 cto a 125 c(t c ) e military temperature only (mto), b 55 cto a 125 c(t c ) the M80C196KB 16-bit microcontroller is a high performance member of the mcs -96 microcontroller family. the M80C196KB is pin-for-pin compatible and uses a true superset of the m8096 instructions. intel's chmos process provides a high performance processor along with low power consumption. to further reduce power requirements, the processor can be placed into idle or powerdown mode. bit, byte, word and some 32-bit operations are available on the M80C196KB. with a 12 mhz oscillator a 16-bit addition takes 0.66 m s, and the instruction times average 0.5 m s to 1.5 m s in typical applications. four high-speed capture inputs are provided to record times when events occur. six high-speed outputs are available for pulse or waveform generation. the high-speed output can also generate four software timers or start an a/d conversion. events can be based on the timer or up/down counter. also provided on-chip are an a/d converter with sample and hold, serial port, watchdog timer, and a pulse- width-modulated output signal. 271089 1 figure 1. M80C196KB block diagram
M80C196KB architecture the M80C196KB is a member of the mcs -96 family, and as such has the same architecture and uses the same instruction set as the m8096. many new features have been added on the M80C196KB including: cpu features divide by 2 instead of divide by 3 clock for 1.5x performance faster instructions, especially indexed/indirect data operations 2.33 m s16 c 16 multiply with 12 mhz clock (was 6.25 m s) on the 8096 faster interrupt response (almost twice as fast as 8096) powerdown and idle modes 6 new instructions including compare long and block move 8 new interrupt vectors/6 new interrupt sources peripheral features sfr window switching allows read-only registers to be written and vice-versa timer2 can count up or down by external selection timer2 has an independent capture register hso line events are stored in a register hso has cam lock and cam clear commands new baud rate values are needed for serial port, higher speeds possible in all modes double buffered serial port transmit register serial port receive overrun and framing error detection pwm has a divide-by-2 prescaler 2
M80C196KB new instructions pusha e pushes the psw, imask, imask1, and wsr (used instead of pushf when new interrupts and registers are used.) assembly language format: pusha object code format: k 11110100 l bytes: 1 states: on-chip stack: 12 off-chip stack: 18 popa e pops the psw, imask, imask1, and wsr (used instead of popf when new interrupts and registers are used.) assembly language format: popa object code format: k 11110101 l bytes: 1 states: on-chip stack: 12 off-chip stack:18 idlpd e sets the part into idle or powerdown mode assembly language format: idlpd y key (key e 1 for idle, key e 2 for powerdown.) object code format: k 11110110 lk key l bytes: 2 states: legal key: 8 illegal key: 25 djnzw e decrement jump not zero using a word counter assembly language format: djnzw wreg, cadd object code format: k 11100001 lk wreg lk disp l bytes: 3 states: jump not taken: 6 jump taken: 10 cmpl e compare 2 long direct values assembly language format: dst src cmpl lreg, lreg object code format: k 11000101 lk src lreg lk dst lreg l bytes: 3 states: 7 bmov e block move using 2 auto-incrementing pointers and a counter assembly language format: ptrs cntreg bmov lreg, wreg object code format: k 11000001 lk wreg lk lreg l bytes: 3 states: internal/internal: 8 per transfer a 6 external/internal: 11 per transfer a 6 external/external: 14 per transfer a 6 3
M80C196KB sfr operation all of the registers that were present on the m8096 work the same way as they did, except that the baud rate value is different. the new registers shown in the memory map control new functions. the most important new register is the window select register (wsr) which allows reading of the formerly write-only registers and vice-versa. using the wsr is described later in this data sheet. 4
M80C196KB packaging the M80C196KB is available in a ceramic pin grid array, shown in figure 2, and a leaded ceramic quad pack shown in figure 3. a comparison of the pinouts for both of these package types is shown in tables 1a 1c. 271089 2 figure 2. pin grid array pinout 5
M80C196KB 271089 3 figure 3. 68-lead ceramic quad flat pack pinout table 1a. M80C196KB pinout e in pga pin order pga signal 1 ach7/p0.7 2 ach6/p0.6 3 ach2/p0.2 4 ach0/p0.0 5 ach1/p0.1 6 ach3/p0.3 7 nmi 8ea 9v cc 10 v ss 11 xtal1 12 xtal2 13 clkout 14 buswidth 15 inst 16 ale/adv 17 rd 18 ad0/p3.0 19 ad1/p3.1 20 ad2/p3.2 21 ad3/p3.3 22 ad4/p3.4 23 ad5/p3.5 pga signal 24 ad6/p3.6 25 ad7/p3.7 26 ad8/p4.0 27 ad9/p4.1 28 ad10/p4.2 29 ad11/p4.3 30 ad12/p4.4 31 ad13/p4.5 32 ad14/p4.6 33 ad15/p4.7 34 t2clk/p2.3 35 ready 36 t2rst/p2.4/ainc 37 bhe /wrh 38 wr /wrl 39 pwm/p2.5 40 t2capture/p2.7/pact 41 v pp 42 v ss 43 hs0.3 44 hs0.2 45 t2up-dn/p2.6 46 p1.7 pga signal 47 p1.6 48 p1.5 49 hso.1 50 hso.0 51 hso.5/hsi.3 52 hso.4/hsi.2 53 hsi.1 54 hsi.0 55 p1.4 56 p1.3 57 p1.2 58 p1.1 59 p1.0 60 txd/p2.0 61 rxd/p2.1 62 reset 63 extint/p2.2 64 v ss 65 v ref 66 angnd 67 ach4/p0.4 68 ach5/p0.5 6
M80C196KB table 1b. M80C196KB pinout e in cqfp pin order cqfp signal 1v cc 2ea 3 nmi 4 ach3/p0.3 5 ach1/p0.1 6 ach0/p0.0 7 ach2/p0.2 8 ach6/p0.6 9 ach7/p0.7 10 ach5/p0.5 11 ach4/p0.4 12 angnd 13 v ref 14 v ss 15 extint/p2.2 16 reset 17 rxd/p2.1 18 txd/p2.0 19 p1.0 20 p1.1 21 p1.2 22 p1.3 23 p1.4 cqfp signal 24 hsi.0 25 hsi.1 26 hso.4/hsi.2 27 hso.5/hsi.3 28 hso.0 29 hso.1 30 p1.5 31 p1.6 32 p1.7 33 t2up-dn/p2.6 34 hso.2 35 hso.3 36 v ss 37 v pp 38 t2capture/p2.7/pact 39 pwm/p2.5 40 wr /wrl 41 bhe /wrh 42 t2rst/p2.4/ainc 43 ready 44 t2clk/p2.3 45 ad15/p4.7 46 ad14/p4.6 cqfp signal 47 ad13/p4.5 48 ad12/p4.4 49 ad11/p4.3 50 ad10/p4.2 51 ad9/p4.1 52 ad8/p4.0 53 ad7/p3.7 54 ad6/p3.6 55 ad5/p3.5 56 ad4/p3.4 57 ad3/p3.3 58 ad2/p3.2 59 ad1/p3.1 60 ad0/p3.0 61 rd 62 ale/adv 63 inst 64 buswidth 65 clkout 66 xtal2 67 xtal1 68 v ss table 1c. M80C196KB pinout e in signal order signal pga cqfp ach0/p0.0 4 6 ach1/p0.1 5 5 ach2/p0.2 3 7 ach3/p0.3 6 4 ach4/p0.4 67 11 ach5/p0.5 68 10 ach6/p0.6 2 8 ach7/p0.7 1 9 p1.0 59 19 p1.1 58 20 p1.2 57 21 p1.3 56 22 p1.4 55 23 p1.5 48 30 p1.6 47 31 p1.7 46 32 txd/p2.0 60 18 rxd/p2.1 61 17 extint/p2.2 63 15 t2clk/p2.3 34 44 t2rst/p2.4/ainc 36 42 pwm/p2.5 39 39 t2up-dn/p2.6 45 33 signal pga cqfp t2capture/p2.7/pact 40 38 ad0/p3.0 18 60 ad1/p3.1 19 59 ad2/p3.2 20 58 ad3/p3.3 21 57 ad4/p3.4 22 56 ad5/p3.5 23 55 ad6/p3.6 24 54 ad7/p3.7 25 53 ad8/p4.0 26 52 ad9/p4.1 27 51 ad10/p4.2 28 50 ad11/p4.3 29 49 ad12/p4.4 30 48 ad13/p4.5 31 47 ad14/p4.6 32 46 ad15/p4.7 33 45 hso.0 50 28 hso.1 49 29 hso.2 44 34 hso.3 43 35 hso.4/hsi.2 52 26 hso.5/hsi.3 51 27 signal pga cqfp hsi.0 54 24 hsi.1 53 25 rd 17 61 wr /wrl 38 40 bhe /wrh 37 41 buswidth 14 64 ale/adv 16 62 ea 82 inst 15 63 ready 35 43 nmi 7 3 reset 62 16 xtal1 11 67 xtal2 12 66 clkout 13 65 angnd 66 12 v ref 65 13 v pp 41 37 v cc 91 v ss 10 68 v ss 42 36 v ss 64 14 7
M80C196KB pin descriptions symbol name and function v cc main supply voltage (5v). v ss digital circuit ground (0v). there are three v ss pins, all of which must be connected. v ref reference voltage for the a/d converter (5v). v ref is also the supply voltage to the analog portion of the a/d converter and the logic used to read port 0. must be connected for a/d and port 0 to function. angnd reference ground for the a/d converter. must be held at nominally the same potential as v ss . v pp timing pin for the return from powerdown circuit. connect this pin with a 1 m f capacitor to v ss anda1m x resistor to v cc . if this function is not used v pp may be tied to v cc . this pin was v bb on the 8x9x-90 parts and is the programming voltage on eprom part. xtal1 input of the oscillator inverter and of the internal clock generator. xtal2 output of the oscillator inverter. clkout output of the internal clock generator. the frequency of clkout is (/2 the oscillator frequency. it has a 50% duty cycle. reset reset input to the chip. input low for at least 4 state times to reset the chip. the subsequent low-to-high transition re- synchronizes clkout and commences a 10-state- time sequence in which the psw is cleared, a byte read from 2018h loads ccr, and a jump to location 2080h is executed. input high for normal operation. reset has an internal pullup. buswidth input for buswidth selection. if ccr bit 1 is a one, this pin selects the bus width for the bus cycle in progress. if buswidth is a 1, a 16-bit bus cycle occurs. if buswidth i sa0an 8-bit cycle occurs. if ccr bit 1 is a 0, the bus is always an 8-bit bus. this pin is the test pin on 8x9x-90 parts. systems with test tied to v cc do not need to change. 8
M80C196KB pin descriptions (continued) symbol name and function nmi a positive transition causes a vector through 203eh. inst output high during an external memory read indicates the read is an instruction fetch. inst is valid throughout the bus cycle. inst is activated only during external memory accesses and output low for a data fetch. ea ea must be equal to a ttl-low to cause address locations 2000h through 3fffh to be directed to off-chip memory. ale/adv address latch enable or address valid output, as selected by ccr. both pin options provide a latch to demultiplex the address from the address/data bus. when the pin is adv , it goes inactive high at the end of the bus cycle. adv can be used as a chip select for external memory. ale/adv is activated only during external memory accesses. rd read signal output to external memory. rd is activated only during external memory reads. wr /wrl write and write low output to external memory, as selected by the ccr. wr will go low for every external write, while wrl will go low only for external writes where an even byte is being written. wr /wrl is activated only during external memory writes. bhe /wrh bus high enable or write high output to external memory, as selected by the ccr. bhe e 0 selects the bank of memory that is connected to the high byte of the data bus. a0 e 0 selects the bank of memory that is connected to the low byte of the data bus. thus accesses to a 16-bit wide memory can be to the low byte only (a0 e 0, bhe e 1), to the high byte only (a0 e 1, bhe e 0), or both bytes (a0 e 0, bhe e 0). if the wrh function is selected, the pin will go low if the bus cycle is writing to an odd memory location. bhe / wrh is valid only during 16-bit external memory write cycles. ready ready input to lengthen external memory cycles, for interfacing to slow or dynamic memory, or for bus sharing. if the pin is high, cpu operation continues in a normal manner. if the pin is low prior to the falling edge of clkout, the memory controller goes into a wait mode until the next positive transition in clkout occurs with ready high. when the external memory is not being used, ready has no effect. internal control of the number of wait states inserted into a bus cycle held not ready is available through configuration of ccr. hsi inputs to high speed input unit. four hsi pins are available: hsi.0, hsi.1, hsi.2, and hsi.3. two of them (hsi.2 and hsi.3) are shared with the hso unit. hso outputs from high speed output unit. six hso pins are available: hso.0, hso.1, hso.2, hso.3, hso.4, and hso.5. two of them (hso.4 and hso.5) are shared with the hsi unit. port 0 8-bit high impedance input-only port. three pins can be used as digital inputs and/or as analog inputs to the on-chip a/d converter. port 1 8-bit quasi-bidirectional i/o port. port 2 8-bit multi-functional port. all of its pins are shared with other functions in the M80C196KB. ports 3 and 4 8-bit bi-directional i/o ports with open drain outputs. these pins are shared with the multiplexed address/data bus which has strong internal pullups. 9
M80C196KB instruction summary mnemonic operands operation (note 1) flags notes z n c v vt st add/addb 2 d w d a a &&&& u b add/addb 3 d w b a a &&&& u b addc/addcb 2 d w d a a a c v &&& u b sub/subb 2 d w d b a &&&& u b sub/subb 3 d w b b a &&&& u b subc/subcb 2 d w d b a a c b 1 v &&& u b cmp/cmpb 2 d b a &&&& u b mul/mulu 2 d,d a 2 w d c a bbbbb b 2 mul/mulu 3 d,d a 2 w b c a bbbbb b 2 mulb/mulub 2 d,d a 1 w d c a bbbbb b 3 mulb/mulub 3 d,d a 1 w b c a bbbbb b 3 divu 2 d w (d,d a 2) /a,d a 2 w remainder bbb & u b 2 divub 2 d w (d,d a 1) /a,d a 1 w remainder bbb & u b 3 div 2 d w (d,d a 2) /a,d a 2 w remainder bbb & u b divb 2 d w (d,d a 1) /a,d a 1 w remainder bbb & u b and/andb 2 d w d and a && 00 bb and/andb 3 d w b and a && 00 bb or/orb 2 d w dora && 00 bb xor/xorb 2 d w d (ecxl. or) a && 00 bb ld/ldb 2 d w a bbbbb b st/stb 2 a w d bbbbb b ldbse 2 d w a; d a 1 w sign(a) bbbbb b 3,4 ldbze 2 d w a; d a 1 w 0 bbbbb b 3,4 push 1 sp w sp b 2; (sp) w a bbbbb b pop 1 a w (sp); sp a 2 bbbbb b pushf 0 sp w sp b 2; (sp) w psw; 0 0 0 0 0 0 psw w 0000h; i w 0 popf 0 psw w (sp); sp w sp a 2; i w & &&&& & & sjmp 1 pc w pc a 11-bit offset bbbbb b 5 ljmp 1 pc w pc a 16-bit offset bbbbb b 5 br [ indirect ] 1pc w (a) bbbbb b scall 1 sp w sp b 2; bbbbb b 5 (sp) w pc; pc w pc a 11-bit offset lcall 1 sp w sp b 2; (sp) w pc; bbbbb b 5 pc w pc a 16-bit offset 10
M80C196KB instruction summary (continued) mnemonic operands operation (note 1) flags notes z n c v vt st ret 0 pc w (sp); sp w sp a 2 bbbb b b j (conditional) 1 pc w pc a 8-bit offset (if taken) bbbb b b 5 jc 1 jump if c e 1 bbbb b b 5 jnc 1 jump if c e 0 bbbb b b 5 je 1 jump if z e 1 bbbb b b 5 jne 1 jump if z e 0 bbbb b b 5 jge 1 jump if n e 0 bbbb b b 5 jlt 1 jump if n e 1 bbbb b b 5 jgt 1 jump if n e 0 and z e 0 bbbb b b 5 jle 1 jump if n e 1orz e 1 bbbb b b 5 jh 1 jump if c e 1 and z e 0 bbbb b b 5 jnh 1 jump if c e 0orz e 1 bbbb b b 5 jv 1 jump if v e 0 bbbb b b 5 jnv 1 jump if v e 1 bbbb b b 5 jvt 1 jump if vt e 1; clear vt bbbb 0 b 5 jnvt 1 jump if vt e 0; clear vt bbbb 0 b 5 jst 1 jump if st e 1 bbbb b b 5 jnst 1 jump if st e 0 bbbb b b 5 jbs 3 jump if specified bit e 1 bbbb b b 5,6 jbc 3 jump if specified bit e 0 bbbb b b 5,6 djnz/ 1 d w d b 1; bbbb b b 5 djnzw if d i 0 then pc w pc a 8-bit offset dec/decb 1 d w d b 1 &&&& u b neg/negb 1 d w 0 b d &&&& u b inc/incb 1 d w d a 1 &&&& u b ext 1 d w d; d a 2 w sign (d) && 00 bb 2 extb 1 d w d; d a 1 w sign (d) && 00 bb 3 not/notb 1 d w logical not (d) && 00 bb clr/clrb 1 d w 0 1000 bb shl/shlb/shll 2 c w msb-----lsb w 0 &&&& u b 7 shr/shrb/shrl 2 0 x msb-----lsb x c &&& 0 b & 7 shra/shrab/shral 2 msb x msb-----lsb x c &&& 0 b & 7 setc 0 c w 1 bb 1 bb b clrc 0 c w 0 bb 0 bb b 11
M80C196KB instruction summary (continued) mnemonic operands operation (note 1) flags notes z n c v vt st clrvt 0 vt w 0 bbbb 0 b rst 0 pc w 2080h 0 0 0 0 0 0 8 di 0 disable all interupts (i w 0) bbbb b b ei 0 enable all interupts (i w 1) bbbb b b nop 0 pc w pc a 1 bbbb b b skip 0 pc w pc a 2 bbbb b b norml 2 left shift till msb e 1; d w shift count && 0 bb b 7 trap 0 sp w sp b 2; bbbb b b 9 (sp) w pc; pc w (2010h) pusha 1 sp w sp-2; (sp) w psw; 0 0 0 0 0 0 psw w 0000h; sp w sp-2; (sp) w imask1/wsr; imask1 w 00h popa 1 imask1/wsr w (sp); sp w sp a 2 &&&& & & psw w (sp); sp w sp a 2 idlpd 1 idle mode if key e 1; bbbb b b powerdown mode if key e 2; chip reset otherwise cmpl 2 d-a &&&& u b bmov 2 [ ptr e hi ] a w [ ptr e low ] a ; bbbb b b until count e 0 notes: 1. if the mnemonic ends in ``b'' a byte operation is performed, otherwise a word operation is done. operands d, b, and a must conform to the alignment rules for the required operand type. d and b are locations in the register file; a can be located anywhere in memory. 2. d,d a 2 are consecutive words in memory; d is double-word aligned. 3. d,d a 1 are consecutive bytes in memory; d is word aligned. 4. changes a byte to word. 5. offset is a 2's complement number. 6. specified bit is one of the 2048 bits in the register file. 7. the ``l'' (long) suffix indicates double-word operation. 8. initiates a reset by pulling reset low. software should re-initialize all the necessary registers with code starting at 2080h. 9. the assembler will not accept this mnemonic. 12
M80C196KB instruction execution state times (minimum) (1) mnemonic direct immed indirect indexed normal * a-inc * short * long * add (3-op) 5 6 7/10 8/11 7/10 8/11 sub (3-op) 5 6 7/10 8/11 7/10 8/11 add (2-op) 4 5 6/8 7/9 6/8 7/9 sub (2-op) 4 5 6/8 7/9 6/8 7/9 addc 4 5 6/8 7/9 6/8 7/9 subc 4 5 6/8 7/9 6/8 7/9 cmp 4 5 6/8 7/9 6/8 7/9 addb (3-op) 5 5 7/10 8/11 7/10 8/11 subb (3-op) 5 5 7/10 8/11 7/10 8/11 addb (2-op) 4 4 6/8 7/9 6/8 7/9 subb (2-op) 4 4 6/8 7/9 6/8 7/9 addcb 4 4 6/8 7/9 6/8 7/9 subcb 4 4 6/8 7/9 6/8 7/9 cmpb 4 4 6/8 7/9 6/8 7/9 mul (3-op) 16 17 18/21 19/22 19/22 20/23 mulu (3-op) 14 15 16/19 17/19 17/20 18/21 mul (2-op) 16 17 18/21 19/22 19/22 20/23 mulu (2-op) 14 15 16/19 17/19 17/20 18/21 div 26 27 28/31 29/32 29/32 30/33 divu 24 25 26/29 27/30 27/30 28/31 mulb (3-op) 12 12 14/17 15/18 15/18 16/19 mulub (3-op) 10 10 12/15 13/15 12/16 14/17 mulb (2-op) 12 12 14/17 15/18 15/18 16/19 mulub (2-op) 10 10 12/15 13/15 12/16 14/17 divb 18 18 20/23 21/24 21/24 22/25 divub 16 16 18/21 19/22 19/22 20/23 and (3-op) 5 6 7/10 8/11 7/10 8/11 and (2-op) 4 5 6/8 7/9 6/8 7/9 or (2-op) 4 5 6/8 7/9 6/8 7/9 xor 4 5 6/8 7/9 6/8 7/9 andb (3-op) 5 5 7/10 8/11 7/10 8/11 andb (2-op) 4 4 6/8 7/9 6/8 7/9 orb (2-op) 4 4 6/8 7/9 6/8 7/9 xorb 4 4 6/8 7/9 6/8 7/9 ld/ldb 4 5 5/8 6/8 6/9 7/10 st/stb 4 5 5/8 6/9 6/9 7/10 ldbse 4 4 5/8 6/8 6/9 7/10 ldbze 4 4 5/8 6/8 6/9 7/10 bmov 6 a 8 per word 6 a 11/14 per word push (int stack) 6 7 9/12 10/13 10/13 11/14 pop (int stack) 8 b 10/12 11/13 11/13 12/14 push (ext stack) 8 9 11/14 12/15 12/15 13/16 pop (ext stack) 11 b 13/15 14/16 14/16 15/17 * times for (internal/external) operands note: 1. execution times for instructions accessing external data memory may be one to two states higher depending on the instruction stream being executed. in sixteen bit mode, the minimum execution state times apply for instructions accessing internal register space. execution times do not reflect eight bit mode or insertion of wait states. 13
M80C196KB instruction execution state times (continued) mnemonic mnemonic pushf (int stack) 6 pushf (ext stack) 8 popf (int stack) 7 popf (ext stack) 10 pusha (int stack) 12 pusha (ext stack) 18 popa (int stack) 12 popa (ext stack) 18 trap (int stack) 16 trap (ext stack) 18 lcall (int stack) 11 lcall (ext stack) 13 scall (int stack) 11 scall (ext stack) 13 ret (int stack) 11 ret (ext stack) 14 cmpl 7 dec/decb 3 clr/clrb 3 ext/extb 4 not/notb 3 inc/incb 3 neg/negb 3 ljmp 7 sjmp 7 br [ indirect ] 7 jnst, jst 4/8 jump not taken/jump taken jnh, jh 4/8 jump not taken/jump taken jgt, jle 4/8 jump not taken/jump taken jnc, jc 4/8 jump not taken/jump taken jnvt, jvt 4/8 jump not taken/jump taken jnv, jv 4/8 jump not taken/jump taken jge, jlt 4/8 jump not taken/jump taken jne, je 4/8 jump not taken/jump taken jbc, jbs 5/9 jump not taken/jump taken djnz 5/9 jump not taken/jump taken djnzw 5/9 jump not taken/jump taken norml 8 a 1 per shift (9 for 0 shift) shrl 7 a 1 per shift (8 for 0 shift) shll 7 a 1 per shift (8 for 0 shift) shral 7 a 1 per shift (8 for 0 shift) shr/shrb 6 a 1 per shift (7 for 0 shift) shl/shlb 6 a 1 per shift (7 for 0 shift) shra/shrab 6 a 1 per shift (7 for 0 shift) clrc 2 setc 2 di 2 ei 2 clrvt 2 nop 2 rst 15 (includes fetch of configuration byte) skip 3 idlpd 8/25 (proper key/improper key) 14
M80C196KB memory map external memory or i/o 0ffffh 4000h internal rom/eprom or external memory 2080h reserved 2040h upper 8 interrupt vectors 2030h rom/eprom security key * 2020h reserved 2019h chip configuration byte 2018h reserved 2014h lower 8 interrupt vectors plus 2 special interrupts 2000h port 3 and port 4 1ffeh external memory or i/o 0100h internal data memory - register file (stack pointer, ram and sfrs) external program code memory 0000h * rom/eprom is available for the 80c196 M80C196KB interrupts number source vector priority location int15 nmi 203eh 15 int14 hsi fifo full 203ch 14 int13 extint pin 203ah 13 int12 timer2 overflow 2038h 12 int11 timer2 capture 2036h 11 int10 4th entry into hsi fifo 2034h 10 int09 ri 2032h 9 int08 ti 2030h 8 special unimplemented opcode 2012h n/a special trap 2010h n/a int07 extint 200eh 7 int06 serial port 200ch 6 int05 software timer 200ah 5 int04 hsi.0 pin 2008h 4 int03 high speed outputs 2006h 3 int02 hsi data available 2004h 2 int01 a/d conversion complete 2002h 1 int00 timer overflow 2000h 0 19h stack pointer 19h stack pointer 18h 18h 17h * ios2 17h pwm e control 16h ios1 16h ioc1 15h ios0 15h ioc0 14h * wsr 14h * wsr 13h * int e mask 1 13h * int e mask 1 12h * int e pend 1 12h * int e pend 1 11h * sp e stat 11h * sp e con 10h port2 10h port2 0fh port1 0fh port1 0fh reserved (1) 0eh port0 0eh baud rate 0eh reserved (1) 0dh timer2 (hi) 0dh timer2 (hi) 0dh * t2 capture (hi) 0ch timer2 (lo) 0ch timer2 (lo) 0ch * t2 capture (lo) 0bh timer1 (hi) 0bh * ioc2 wsr e 15 0ah timer1 (lo) 0ah watchdog 09h int e pending 09h int e pending other sfrs in wsr 08h int e mask 08h int e mask 15 become readable 07h sbuf(rx) 07h sbuf(tx) if they were writable 06h hsi e status 06h hso e command in wsr e 0 and writable 05h hsi e time (hi) 05h hso e time (hi) if they were readable 04h hsi e time (lo) 04h hso e time (lo) in wsr e 0 03h ad e result (hi) 03h hsi e mode 02h ad e result (lo) 02h ad e command * new or changed 01h zero reg (hi) 01h zero reg (hi) register function 00h zero reg (lo) 00h zero reg (lo) note: when read when written 1. reserved registers should not be written. wsr e 0 15
M80C196KB using the alternate register window (wsr e 15) i/o register expansion on the new chmos members of the mcs-96 family has been provided by making two register windows available. switching between these windows is done using the window select register (wsr). the pusha and popa instructions can be used to push and pop the wsr and second interrupt mask when entering or leaving interrupts, so it is easy to change between windows. on the M80C196KB only window 0 and window 15 are active. window 0 is a true superset of the standard 8096 sfr space, while window 15 allows the read-only registers to be written and write-only registers to be read. the only major exception to this is the timer2 register which is the timer2 capture register in window 15. the writeable register for timer2 is in window 0. there are also some minor changes and cautions. the descriptions of the registers which have different functions in window 15 than in window 0 are listed below: ad e command (02h) e read the last written command ad e result (02h, 03h) e write a value into the result register hsi e mode (03h) e read the value in hsi e mode hsi e time (04h,05h) e write to fifo holding register hso e time (04h,05h) e read the last value placed in the holding register hsi e status (06h) e write to status bits but not to hsi pin bits. (pin bits are 1,3,5,7). hso e command (06h) e read the last value placed in the holding register sbuf(rx) (07h) e write a value into the receive buffer sbuf(tx) (07h) e read the last value written to the transmit buffer watchdog(0ah) e read the value in the upper byte of the wdt timer1 (0ah,0bh) e write a value to timer1 timer2 (0ch,0dh) e read/write the timer2 capture register. note that timer2 read/write is done with wsr e 0. ioc2 (0bh) e last written value is readable, except bit 7 (note 1) baud e rate (0eh) e no function, cannot be read port0 (0eh) e no function, no output drivers on the pins. register reserved. port1 e ioport1 cannot be read or written in window 15. register reserved. sp e stat (11h) e set the status bits, ti and ri can be set, but it will not cause an interrupt sp e con (11h) e read the current control byte ios0 (15h) e writing to this register controls the hso pins. bits 6 and 7 are inactive for writes. ioc0 (15h) e last written value is readable, except bit 1 (note 1) ios1 (16h) e writing to this register will set the status bits, but not cause interrupts. bits 6 and 7 are not functional ioc1 (16h) e last written value is readable ios2 (17h) e writing to this register will set the status bits, but not cause interrupts. pwm e control (17h) e read the duty cycle value written to pwm e control note: 1. ioc2.7 (cam clear) and ioc0.1 (t2rst) are not latched and will read as a 1 (precharged bus) . being able to write to the read-only registers and vice-versa provides a lot of flexibility. one of the most useful advantages is the ability to set the timers and hso lines for initial conditions other than zero. reserved registers may be used for testing as future features. do not write to these registers. read from reserved registers will return indeterminate values. 16
M80C196KB sfr bit summary a summary of the sfrs which control i/o functions has been included in this section. the summary is separated into a list of those sfrs which have changed on the M80C196KB and a list of those which have remained almost the same. the following M80C196KB sfrs are different than those on the m8096bh: (the read and write comments indicate the register's function in window 0 unless otherwise specified.) sbuf(tx): now double buffered 07h write uses new baud rate values baud rate: 0eh write sp e stat: 76543210 rb8/ ri ti fe txe oe x x rpe 11h rpe : receive parity error read ri : receive indicator ti : transmit indicator fe : framing error txe : transmitter empty oe : receive overrun error ipend1: 76543210 imask1: nmi fifo ext t2 t2 hsi4 ri ti full int ovf cap 12h,13h nmi : non-maskable interrupt (set to 0 for future compatibility) read/write fifo full : hsio fifo full extint : external interrupt pin t2ovf : timer2 overflow t2cap : timer2 capture hsi4 : hsi has 4 or more entries in fifo ri : receive interrupt ti : transmit interrupt 17
M80C196KB wsr: 76543210 0 0 0 0 wwww 14h read/write wwww e 0 : sfrs function like a superset of m8096 sfrs wwww e 14 : ppw register wwww e 15 : exchange read/write registers wwww e other : undefined, do not use 0000 : these bits must always be written as zeros to provide compatibility with future products. ios2: 76543210 start t2 hso.5 hso.4 hso.3 hso.2 hso.1 hso.0 a2d reset 17h read indicates which hso event occured start a2d : hso e cmd 15, start a to d t2reset : hso e cmd 14, timer 2 reset hso.0-5 : output pins hso.0 through hso.5 ioc2: 76543210 clear ena t2alt a2d x slow t2ud fast cam lock int cpd pwm ena t2en 0bh clear e cam : clear entire cam write ena e lock : enable lockable cam entry feature t2alt int : enable t2 alternate interrupt at 8000h a2d e cpd : clock prescale disable for low xtal frequency (a to d conversion in fewer state times) x : set to 0 slow e pwm : turn on divide by 2 prescaler on pwm t2ud ena : enable timer 2 as up/down counter fast e t2en : enable fast increment of t2; once per state time. the following registers are the same on the M80C196KB as they were on the m8096bh: a/d result lo (02h) 271089 4 a/d command (02h) 271089 5 18
M80C196KB chip configuration (2018h) 271089 6 * minor change hsi e mode (03h) 271089 7 hsi e status (06h) 271089 8 hso command (06h) 271089 9 * minor change spcon (11h) 271089 10 ios0 (15h) 271089 11 19
M80C196KB ioc0 (15h) 271089 12 ios1 (16h) 271089 13 ioc1 (16h) 271089 14 port 2 multiple functions pin func. alternative control function reg. 2.0 output txd (serial port ioc1.5 transmit) 2.1 input rxd (serial port spcon.3 receive) 2.3 input t2clk (timer2 clock ioc0.7 & baud) 2.4 input t2rst (timer2 reset) ioc0.5 2.5 output pwm output ioc1.0 2.6 qbd * timer2 up/ ioc2.1 down select 2.7 qbd * timer2 capture n/a * qbd e quasi-bidirectional baud rate calculations asynchronous modes 1, 2 and 3: baud e reg e xtal1 baud rate c 16 b 1or t2clk baud rate c 8 synchronous mode 0: baud e reg e xtal1 baud rate c 2 b 1or t2clk baud rate baud rates and baud register values baud xtal frequency rate 8.0 mhz 10.0 mhz 12.0 mhz 300 1666 b 0.02 2082 0.02 2499 0.00 1200 416 b 0.08 520 b 0.03 624 0.00 2400 207 0.16 259 0.16 312 b 0.16 4800 103 b 0.16 129 0.16 155 0.16 9600 51 b 0.16 64 0.16 77 0.16 19.2k 25 0.16 32 1.40 38 0.16 baud register value/% error a maximum baud rate of 750 kbaud is available in the asynchronous modes with 12 mhz on xtal1. the synchronous mode has a maximum rate of 3.0 mbaud with a 12 mhz clock. location 0eh is the baud register. it is loaded sequentially in two bytes, with the low byte being loaded first. this register may not be loaded with zero in serial port mode 0. note: the maximum t2clk rate is 3 mhz when used to set the baud rate. 20
M80C196KB electrical characteristics absolute maximum ratings * case temperature under bias b 55 cto a 125 c storage temperature b 65 cto a 150 c voltage on any pin to v ss b 0.5v to a 7.0v power dissipation1.5w notice: this data sheet contains preliminary infor- mation on new products in production. the specifica- tions are subject to change without notice. verify with your local intel sales office that you have the latest data sheet before finalizing a design. * warning: stressing the device beyond the ``absolute maximum ratings'' may cause permanent damage. these are stress ratings only. operation beyond the ``operating conditions'' is not recommended and ex- tended exposure beyond the ``operating conditions'' may affect device reliability. operating conditions mil-std-883 symbol description min max units t c case temperature (instant on) b 55 a 125 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v f osc oscillator frequency 3.5 12 mhz military temperature (mto) symbol description min max units t c case temperature (instant on) b 55 a 125 c v cc digital supply voltage 4.50 5.50 v v ref analog supply voltage 4.50 5.50 v f osc oscillator frequency 3.5 12 mhz note: angnd and v ss should be nominally at the same potential. dc characteristics (over specified operating conditions) symbol description min max units comments v il input low voltage b 0.5 0.8 v v ih input high voltage (note 1) 0.2 v cc a 1.0 v cc v v ih1 input high voltage on xtal 1 0.7 v cc v cc v v ih2 input high voltage on reset 2.2 v cc v v ol output low voltage 0.3 v i ol e 200 m a 0.45 v i ol e 3.2 ma 1.5 v i ol e 7ma v oh output high voltage v cc b 0.3 v i oh eb 200 m a (standard outputs) (note 2) v cc b 0.7 v i oh eb 3.2 ma v cc b 1.5 v i oh eb 7ma v oh1 output high voltage v cc b 0.3 v i oh eb 10 m a (quasi-bidirectional outputs) (note 3) v cc b 0.7 v i oh eb 30 m a v cc b 1.5 v i oh eb 60 m a notes: 1. all pins except reset and xtal1. 2. standard outputs include ad0 15, rd ,wr , ale, bhe , inst, hso pins, pwm/p2.5, clkout, reset, ports 3 and 4, txd/p2.0, and rxd (in serial mode 0). the v oh specification is not valid for reset. ports 3 and 4 are open-drain outputs. 3. qbd (quasi-bidirectional) pins include port 1, p2.6 and p2.7. 21
M80C196KB dc characteristics (over specified operating conditions) (continued) symbol description min max units comments i li input leakage current (std. inputs) (note 4) g 10 m a0 k v in k v cc b 0.3v i li1 input leakage current () g 7ma0 k v in k v ref i tl 1 to 0 transition current (qbd pins) (note 3) b 800 m av in e 2.0v i il logical 0 input current (qbd pins) (note 3) b 50 m av in e 0.45v i il1 logical 0 input current in reset (note 5) b 850 m av in e 0.45 v (ale, rd ,wr , bhe , inst, p2.0) i cc active mode current in reset 60 ma xtal1 e 12 mhz i ref a/d converter reference current 5 ma v cc e v pp e v ref e 5.5v i idle idle mode current 25 ma i cc1 active mode current 30 ma xtal1 e 3.5 mhz i pd powerdown mode current 50 m av cc e v pp e v ref e 5.5v, xtal1 e 12 mhz r rst reset pullup resistor 6k 50k x c s pin capacitance (any pin to v ss )10pff test e 1.0 mhz notes: (notes apply to all specifications) 2. standard outputs include ad0 15, rd ,wr , ale, bhe , inst, hso pins, pwm/p2.5, clkout, reset, ports 3 and 4, txd/p2.0, and rxd (in serial mode 0). the v oh specification is not valid for reset. ports 3 and 4 are open-drain outputs. 3. qbd (quasi-bidirectional) pins include port 1, p2.6 and p2.7. 4. standard inputs include hsi pins, ea , ready, buswidth, nmi, rxd/p2.1, extint/p2.2, t2clk/p2.3, and t2rst/ p2.4. 5. holding these pins below v ih in reset may cause the part to enter test modes. 6. maximum current per pin must be externally limited to the following values if v ol is held above 0.45v or v oh is held below v cc b 0.7v: i ol on output pins: 10 ma i oh on quasi-bidirectional pins: self limiting i oh on standard output pins: 10 ma 7. maximum current per bus pin (data and control) during normal operation is g 3.2 ma. 8. during normal (non-transient) conditions the following total current limits apply: port 1, p2.6 i ol :29ma i oh is self limiting hso, p2.0, rxd, reset i ol :29ma i oh :26ma p2.5, p2.7, wr , bhe i ol :13ma i oh :11ma ad0 ad15 i ol :52ma i oh :52ma rd , ale, inst clkout i ol :13ma i oh :13ma 271089 16 figure 4. i cc and i idle vs frequency 22
M80C196KB ac characteristics (over specified operating conditions) test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 12 mhz the system must meet these specifications to work with the M80C196KB: symbol description min max units notes t avyv address valid to ready setup 2t osc b 85 ns t llyv ale low to ready setup M80C196KB t osc b 75 ns t ylyh non ready time no upper limit ns t clyx ready hold after clkout low 0 t osc b 30 ns (note 1) t llyx ready hold after ale low t osc b 15 2t osc b 40 ns (note 1) t avgv address valid to buswidth setup 2t osc b 85 ns t llgv ale low to buswidth setup t osc b 70 ns t clgx buswidth hold after clkout low 0 ns t avdv address valid to input data valid M80C196KB 3t osc b 67 ns t rldv rd active to input data valid M80C196KB t osc b 23 ns t cldv clkout low to input data valid t osc b 50 ns t rhdz end of rd to input data float t osc b 20 ns t rxdx data hold after rd inactive 0 ns note: 1. if max is exceeded, additional wait states will occur. 23
M80C196KB ac characteristics (over specified operating conditions) (continued) test conditions: capacitive load on all pins e 100 pf, rise and fall times e 10 ns, f osc e 12 mhz the M80C196KB will meet these specifications: symbol description min max units notes f xtal frequency on xtal 1 M80C196KB 3.5 12 mhz t osc i/f xtal M80C196KB 83 286 ns t xhch xtal1 high to clkout high or low 20 110 ns t clcl clkout cycle time 2t osc ns t chcl clkout high period t osc b 10 t osc a 10 ns t cllh clkout falling edge to ale rising b 10 10 ns t llch ale falling edge to clkout rising b 15 15 ns t lhlh ale cycle time 4t osc ns t lhll ale high period t osc b 12 t osc a 12 ns t avll address setup to ale falling edge t osc b 20 ns t llax address hold after ale falling edge t osc b 40 ns t llrl ale falling edge to rd falling edge t osc b 40 ns t rlcl rd low to clkout falling edge 4 25 ns t rlrh rd low period t osc b 5ns t rhlh rd rising edge to ale rising edge t osc t osc a 25 ns (note 2) t rlaz rd low to address float 10 ns t llwl ale falling edge to wr falling edge t osc b 10 ns t clwl clkout low to wr falling edge 0 25 ns t qvwh data stable to wr rising edge M80C196KB t osc b 23 ns t chwh clkout high to wr rising edge b 515ns t wlwh wr low period t osc b 30 ns t whqx data hold after wr rising edge t osc b 15 ns t whlh wr rising edge to ale rising edge t osc b 15 t osc a 10 ns (note 2) t whbx bhe , inst hold after wr rising edge t osc b 15 ns note: 2. assuming back-to-back bus cycles. 24
M80C196KB system bus timings 271089 17 271089 18 25
M80C196KB external clock drive symbol parameter min max units 1/t xlxl oscillator frequency M80C196KB 3.5 12.0 mhz t xlxl oscillator period M80C196KB 83 286 ns t xhxx high time 32 ns t xlxx low time 32 ns t xlxh rise time 10 ns t xhxl fall time 10 ns external clock drive waveforms 271089 19 ac testing input, output waveforms 271089 20 ac testing inputs are driven at 2.4v for a logic ``1'' and 0.45v for a logic ``0'' timing measurements are made at 2.0v for a logic ``1'' and 0.8v for a logic ``0''. float waveforms 271089 21 for timing purposes a port pin is no longer floating when a 100 mv change from load voltage occurs and begins to float when a 100 mv change from the loaded v oh /v ol level occurs i ol /i oh e g 15 ma. explanation of ac symbols each symbol is two pairs of letters prefixed by ``t'' for time. the characters in a pair indicate a signal and its condition, respectively. symbols represent the time between the two signal/condition points. conditions: h - high l - low v - valid x - no longer valid z - floating signals: a - address b - bhe c - clkout d - data g - buswidth l - ale/adv r-rd w-wr /wrh /wrl x - xtal1 y - ready 26
M80C196KB ac characteristicseserial porteshift register mode serial port timingeshift register mode symbol parameter min max units t xlxl serial port clock period (brr t 8002h) 6 t osc ns t xlxh serial port clock falling edge 4 t osc b 50 4 t osc a 50 ns to rising edge (brr t 8002h) t xlxl serial port clock period (brr e 8001h) 4 t osc ns t xlxh serial port clock falling edge 2 t osc b 50 2 t osc a 50 ns to rising edge (brr e 8001h) t qvxh output data setup to clock rising edge 2 t osc b 50 ns t xhqx output data hold after clock rising edge 2 t osc b 50 ns t xhqv next output data valid after clock rising edge 2 t osc a 50 ns t dvxh input data setup to clock rising edge t osc a 50 ns t xhdx input data hold after clock rising edge 0 ns t xhqz last clock rising to output float t osc ns waveformeserial porteshift register mode serial port waveformeshift register mode 271089 22 27
M80C196KB a to d characteristics there are two modes of a/d operation: with or with- out clock prescaler. the speed of the a/d converter can be adjusted by setting a clock prescaler on or off. at high frequencies more time is needed for the comparator to settle. the maximum frequency with the clock prescaler disabled is 8 mhz. the conver- sion times with the prescaler turned on or off is shown in the table below. the converter is ratiometric, so the absolute accuracy is directly dependent on the accuracy and stability of v ref .v ref must be close to v cc since it supplies both the resistor ladder and the digital sec- tion of the converter. a/d converter specifications the specifications given below assume adherence to the operating conditions section of this data sheet. testing is performed in mode 2 with v ref e 5.12v and 12 mhz on xtal1. clock prescaler on clock prescaler off ioc2.4 e 0 ioc2.4 e 1 mode 0 158 states mode 2 91 states 26.33 m s @ 12 mhz 22.75 m s @ 8 mhz a/d characteristics (over specified operating conditions) parameter typical * (1) minimum maximum units ** notes resolution 256 1024 levels 10 bits absolute error 0 g 4 lsbs full scale error b 0.5 g 0.5 lsbs zero offset error g 0.5 lsbs non-linearity 0 g 4 lsbs differential non-linearity 0 g 2 lsbs channel-to-channel matching 0 g 1 lsbs repeatability g 0.25 lsbs temperature coefficients: offset 0.009 lsb/ c full scale 0.009 lsb/ c differential non-linearity 0.009 lsb/ c off isolation b 60 db 2, 3 feedthrough b 60 db 2 v cc power supply rejection b 60 db 2 input resistance 750 1.2k x dc input leakage 0 3.0 m a sample time slow mode 15 states 4 fast mode 8 states 4 input capacitance 3 pf notes: * an ``lsb'', as used here, has a value of approximately 5 mv. 1. these values are expected for most parts at 25 c but are not tested or guaranteed. 2. dc to 100 khz. 3. multiplexer break-before-make guaranteed. 4. one state e 167 ns at 12 mhz, 250 ns at 8 mhz. 28
M80C196KB a/d glossary of terms absolute errore the maximum difference be- tween corresponding actual and ideal code tran- sitions. absolute error accounts for all deviations of an actual converter from an ideal converter. actual characteristice the characteristic of an actual converter. the characteristic of a given converter may vary over temperature, supply volt- age, and frequency conditions. an actual character- istic rarely has ideal first and last transition locations or ideal code widths. it may even vary over multiple conversions under the same conditions. break-before-makee the property of multi- plexer which guarantees that a previously selected channel will be deselected before a new channel is selected (e.g., the converter will not short inputs to- gether). channel-to-channel matchinge the differ- ence between corresponding code transitions of ac- tual characteristics taken from different channels un- der the same temperature, voltage and frequency conditions. characteristice a graph of input voltage ver- sus the resultant output code for an a/d converter. it describes the transfer function of the a/d convert- er. codee the digital value output by the converter. code transitione the point at which the con- verter changes from an output code of q, to a code of q a 1. the input voltage corresponding to a code transition is defined to be that voltage which is equally likely to produce either of two adjacent codes. code widthe the voltage corresponding to the difference between two adjacent code transitions. dc input leakagee leakage current to ground from an analog input pin. differential non-linearitye the difference between the ideal and actual code widths of the ter- minal based characteristic. feedthroughe attenuation of a voltage applied on the selected channel of the a/d converter after the sample window closes. full scale errore the difference between the expected and actual input voltage corresponding to the full scale code transition. ideal characteristice a characteristic with its first code transition at v in e 0.5 lsb, its last code transition at v in e (v ref b 1.5 lsb) and all code widths equal to one lsb. input resistancee the effective series resist- ance from the analog input pin to the sample capaci- tor. lsbeleast significant bit: the voltage corre- sponding to the full scale voltage divided by 2 n , where n is the number of bits of resolution of the converter. for an 8-bit converter with a reference voltage of 5.12v, one lsb is 20 mv. note that this is different than digital lsbs, since an uncertainty of two lsb, when referring to an a/d converter, equals 40 mv. (this has been confused with an uncertainty of two digital bits, which would mean four counts, or 80 mv.) non-linearitye the maximum deviation of code transitions of the terminal based characteristic from the corresponding code transitions of the ideal char- acteristic. off-isolatione attenuation of a voltage applied on a deselected channel of the a/d converter. (also referred to as crosstalk.) repeatabilitye the difference between corre- sponding code transitions from different actual char- acteristics taken from the same converter on the same channel at the same temperature, voltage and frequency conditions. resolutione the number of input voltage levels that the converter can unambiguously distinguish between. also defines the number of useful bits of information which the converter can return. sample timee begins when the sample capacitor is attached to a selected channel and ends when the sample capacitor is disconnected from the se- lected channel. temperature coefficientse change in the stated variable per degree centigrade temperature change. temperature coefficients are added to the typical values of a specification to see the effect of temperature drift. terminal based characteristice an actual characteristic which has been rotated and translated to remove zero offset and full scale error. v cc rejectione attenuation of noise on the v cc line to the a/d converter. zero offsete the difference between the ex- pected and actual input voltage corresponding to the first code transition. 29
M80C196KB M80C196KB functional deviations the M80C196KB has the following problems. 1. the djnzw instruction is guaranteed to be func- tional. the djnz (byte instruction) work around is no longer needed. 2. the serial port only tolerates a a 1.25%, b 7.5% baud rate error between transmitter and receiv- er. if the serial port fails on the receiver, increase the baud rate. 3. the hsi unit has two errata: one dealing with res- olution and the other with first entries into the fifo. the hsi resolution is 9 states instead of 8 states. events on the same line may be lost if they occur faster than once every 9 state times. there is a mismatch between the 9 state time hsi resolution and the 8 state time timer. this causes one time value to be unused every 9 timer counts. events may receive a time-tag one count later than expected because of this ``skipped'' time val- ue. if the first two events into an empty fifo (not including the holding register) occur in the same internal phase, both are recorded with one time- tag. otherwise, if the second event occurs within 9 states after the first, its time-tag is one count later than the first's. if this is the ``skipped'' time value, the second event's time-tag is 2 counts lat- er than the first's. if the fifo and holding register are empty, the first event will transfer into the holding register after 8 state times, leaving the fifo empty again. if the second event occurs after this time, it will act as a new first event into an empty fifo. 4. the serial port framing error flag that failed to in- dicate an error if the bit preceding the stop bit is a 1 has been fixed. converting from other m8097 family products to the M80C196KB the following list of suggestions for designing an m809xbh system will yield a design that is easily converted to the M80C196KB. 1. do not base critical timing loops on instruction or peripheral execution times. 2. use equate statements to set all timing parame- ters, including the baud rate. 3. do not base hardware timings on clkout or xtal1. the timings of the M80C196KB are differ- ent than those of the m8x9xbh, but they will function with standard rom/eprom/peripheral type memory systems. 4. make sure all inputs are tied high or low and not left floating. 5. indexed and indirect operations relative to the stack pointer (sp) work differently on the M80C196KB than on the m8097. on the m8097, the address is calculated based on the un-updat- ed version of the stack pointer. the M80C196KB uses the updated version. the offset for push [ sp ] , pop [ sp ] , push nn [ sp ] and pop nn [ sp ] instructions may need to be changed by a count of 2. 30

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